The technical field is resistive cross point memory devices. More specifically, the technical field is memory devices having short read times.
Magnetic Random Access Memory (xe2x80x9cMRAMxe2x80x9d) is a proposed type of non-volatile memory. Accessing data from MRAM devices is much faster than accessing data from conventional long term storage devices such as hard drives. Additionally, MRAM is compact and consumes less power than conventional long term storage devices.
FIG. 1 illustrates a conventional MRAM memory array 10 having resistive memory cells 12 located at cross points of word lines 14 and bit lines 16. The word lines 14 extend horizontally along rows of the memory array 10, and the bit lines 16 extend vertically along columns of the memory array 10. Each memory cell 12 is capable of storing the binary states of xe2x80x9c1xe2x80x9d and xe2x80x9c0.xe2x80x9d
FIG. 2 illustrates a conventional memory cell 12. The memory cell 12 is a spin dependent tunneling (xe2x80x9cSDTxe2x80x9d) device. The memory cell 12 includes a pinned layer 24 and a free layer 18. The pinned layer 24 has a magnetization that has a fixed orientation, illustrated by the arrow 26. The magnetization of the free layer 18, illustrated by the bidirectional arrow 28, can be oriented in either of two directions along an xe2x80x9ceasy axisxe2x80x9d of the free layer 18. If the magnetizations of the free layer 18 and the pinned layer 24 are in the same direction, the orientation of the memory cell 12 is xe2x80x9cparallel.xe2x80x9d If the magnetizations are in opposite directions, the orientation is xe2x80x9canti-parallel.xe2x80x9d The two orientations correspond to the binary states of xe2x80x9c1xe2x80x9d and xe2x80x9c0,xe2x80x9d respectively.
The free layer 18 and the pinned layer 24 are separated by an insulating tunnel barrier layer 20. The insulating tunnel barrier layer 20 allows quantum mechanical tunneling to occur between the free layer 18 and the pinned layer 24. The tunneling is electron spin dependent, making the resistance of the memory cell 12 a function of the relative orientations of the magnetizations of the free layer 18 and the pinned layer 24. The resistance of the memory cell 12 has a xe2x80x9clowxe2x80x9d value of R if the orientation is parallel, and a xe2x80x9chighxe2x80x9d value of R+xcex94R if the orientation is anti-parallel.
Each memory cell 12 in the memory array 10 can have its binary state changed by a write operation. Write currents supplied to the word line 14 and the bit line 16 crossing at a specific memory cell 12 switch the magnetization of the free layer 18 between parallel and anti-parallel with the pinned layer 24. A current Iy passing through the bit line 16 results in the magnetic field Hx. A similar magnetic field Hy is created when a current Ix passes through the word line 14. The magnetic fields Hx and Hy combine to switch the magnetic orientation of the memory cell 12. The change in resistance due to the changing memory cell magnetization is readable to determine the binary state of the memory cell 12.
Each of the bit lines 16 in the memory array 10 is connected to a switch (not shown), and each switch is connected to an input of a sense amplifier (not shown). The binary state, or xe2x80x9cbit,xe2x80x9d of a selected memory cell 12 is read by applying a read voltage to the word line 14 of a particular memory cell 12 while the bit line 16 crossing the memory cell 12 is connected to the input of the sense amplifier. The switch connecting the selected bit line 16 to the sense amplifier is alternately opened and closed to read the selected memory cell 12.
The read operation in the conventional memory array 10 is slowed by the requirement for the memory array 10 to xe2x80x9csettlexe2x80x9d between reading memory cells 12. The memory array 10 must settle because each time a switch connecting a selected bit line 16 to the sense amplifier is opened or closed, the potential at the end of the bit line 16 changes. The change in potential at the end of the bit line causes the voltage across the memory cells 12 to change to a different equilibrium state. The microprocessor controlling the read operation must therefore incorporate a settling time into the read operation to allow the memory array 10 to settle to the desired equilibrium state between reading of memory cells 12. A settling time is undesirable because fewer memory cells 12 can be read per unit time.
A need therefore exists to decrease the read time in memory arrays.
According to a first aspect, a memory device achieves a reduced read time. The memory device includes a memory array of memory cells, and intersecting word lines and bit lines. A bank of sense amplifier select switches selectively couples the bit lines to a sense amplifier. Each switch in the bank of sense amplifier select switches may be closed to allow the sense amplifier to sense the binary state of a selected memory cell. A bank of read/write select switches selectively couples the bit lines to a column write current source, and to a reference potential voltage. The switches in the bank of read/write select switches may each be closed to couple a selected bit line to the reference potential voltage. During read operations, the bank of sense amplifier select switches and the bank of read/write select switches are operated so that the bit lines in the memory array remain in an equipotential state.
According to the first aspect, the array is not disturbed by the connection and disconnection of bit lines with the sense amplifier. The sense amplifier, which is set at the reference potential voltage, provides the same potential to the bit lines as the bank of read/write switches. Because the bit lines in the memory array are not disturbed from the equipotential state, a settling time due to switching to the amplifier is not required. Read times are therefore shorter than in conventional devices.